1. Field of the Invention
The present invention relates to an optical receiver and an optical reception method, for demodulating a signal light subjected to the differential quadrature phase shift keying, and in particular, to a technology for realizing a stably operated optical receiver of a small size.
2. Description of the Related Art
In recent years, as a technology enabling the high bit rate optical transmission at 40 Gb/s or higher, there has been noticed an optical modulation system, such as a differential phase shift keying (DPSK) system, a differential quadrature phase shift keying (DQPSK) system or the like. The DQPSK system has a more excellent characteristic in terms of the long distance transmission, the dense multiplexing/large capacity, and the design performance, usability and the like, in comparison with a known optical modulation system, such as, a typical non-return to zero (NRZ) modulation system, a CS-RZ modulation system, a RZ-DPSK modulation system or the like. The DQPSK system in the specification of the present invention includes the RZ-DQPSK system in which a DQPSK signal is return to zero (RZ) pulsed, and a carrier-suppressed (CS) RZ-DQPSK system.
Here, there will be briefly described an optical sender and an optical receiver, to which the DQPSK system is applied.
As the optical sender applied with the DQPSK system, there has been known an optical sender provided with a basic configuration as shown in FIG. 4 for example, (refer to Japanese National Phase Publication No. 2004-516743 and the literature: A. H. Gnauck et al., “Spectrally Efficient (0.8 b/s/Hz) 1-Tb/s (25×42.7 Gb/s) RZ-DQPSK Transmission Over 28 100-km SSMF Spans With 7 Optical Add/Drops”, ECOC 2004, PD. 4.4.1).
In this optical sender, a continuous light emitted from a light source 101 is branched into two. One of the branched lights is given to a phase modulator (PM) 102, and the other branched light is given to a phase modulator (PM) 103 and also to a phase shifter 104. The phase modulators 102 and 103 are driven independently from each other in accordance with modulating signals Ik and Qk generated by processing different data signals uk and vk by a pre-coder (integrator) 105, to selectively change phases of the lights input thereto by 0 or π [rad]. The light propagated through an optical path on the side of the phase modulator 103 is given with a phase difference of π/2 by the phase shifter 104 relative to the light propagated through an optical path on the side of the phase modulator 102. Therefore, an output light from the optical path on the side of the phase modulator 102 becomes an optical signal obtained by modulating the light from the light source 101 by the phase deviation of 0 or π, whereas an output light from the optical path on the side of the phase modulator 103 becomes an optical signal obtained by modulating the light from the light source 101 by the phase deviation of π/2 or 3π/2. Then, the output lights from the respective optical paths are multiplexed, so that a DQPSK signal light whose phase is changed by four values of π/4, 3π/4, 5π/4 and 7π/4, is generated. The bit rate of the DQPSK signal light becomes twice the bit rate of each of the data signals uk and vk processed by the pre-coder 105. Therefore, for example in order to transmit the DQPSK signal light of 40 Gb/s, the respective phase modulators 102 and 103 may be driven using the data signals of 20 Gb/s.
Note, a configuration of the pre-coder 105 corresponds to the logical expression shown in the next formula (1).
                                          I            k                    =                                                    (                                                                            u                      k                                        ⊕                                          I                                              k                        -                        1                                                                              _                                )                            ⁢                              (                                                      u                    k                                    ⊕                                      Q                                          k                      -                      1                                                                      )                            ⁢                              (                                                      I                                          k                      -                      1                                                        ⊕                                      Q                                          k                      -                      1                                                                      )                                      +                                          (                                                                            v                      k                                        ⊕                                          I                                              k                        -                        1                                                                              _                                )                            ⁢                              (                                                      v                    k                                    ⊕                                                            Q                                              k                        -                        1                                                              _                                                  )                            ⁢                              (                                                      I                                          k                      -                      1                                                        ⊕                                                            Q                                              k                        -                        1                                                              _                                                  )                                                    ⁢                                  ⁢                              Q            k                    =                                                    (                                                                            v                      k                                        ⊕                                          Q                                              k                        -                        1                                                                              _                                )                            ⁢                              (                                                      v                    k                                    ⊕                                      I                                          k                      -                      1                                                                      )                            ⁢                              (                                                      I                                          k                      -                      1                                                        ⊕                                      Q                                          k                      -                      1                                                                      )                                      +                                          (                                                                            u                      k                                        ⊕                                          Q                                              k                        -                        1                                                                              _                                )                            ⁢                              (                                                      u                    k                                    ⊕                                                            I                                              k                        -                        1                                                              _                                                  )                            ⁢                              (                                                                            I                                              k                        -                        1                                                              _                                    ⊕                                      Q                                          k                      -                      1                                                                      )                                                                        (        1        )            
In the above logical expression, Ik, Qk, vk and uk are logical values (1 or 0) in kth clock timing at respective sites within the pre-coder typically shown in FIG. 4, and the suffix k−1 indicates a logical value before one clock. In order to realize this relationship, in the configuration example of FIG. 4, Ik and Qk are fed back within the pre-coder via one symbol-time delay τ.
Further, as shown in a configuration of FIG. 5 for example, the above DQPSK signal light is given to an intensity modulator 106 which is driven based on a clock signal CLK having a duty ratio of 50%, which is synchronized with the data signal, to be RZ pulsed, so that a RZ-DQPSK signal light is generated. Further, the duty ratio of the clock signal CLK is set to 66% or the like, so that a CSRZ-DQPSK signal light is generated. The intensity and a phase of the RZ-DQPSK signal light are in a relationship as shown in FIG. 6 for example.
As a conventional optical receiver demodulating the DQPSK signal light, there has been known a configuration as shown in FIG. 7 for example (refer to Japanese National Publication No. 2004-516743). In this optical receiver, the input DQPSK signal light is branched into two, and the branched lights are given to delay interferometers 201 and 202, respectively. The delay interferometers 201 and 202 each has a configuration in which, by making the optical path lengths of two arms of a Mach-Zehnder optical waveguide which is formed on, for example, a silica substrate, an indium phosphide substrate or the like, different from each other, a relative delay time difference corresponding to one symbol of modulated code can be generated between the lights propagated through the respective arms. Further, an interference operating point of the delay interferometer 201 is set to π/4 by a phase shifting section 203 formed on one of the arms, and an interference operating point of the delay interferometer 202 is set to −π/4 by a phase shifting section 204 formed on the other arm. Complementary two output powers output from an output stage coupler of the delay interferometer 201 is received by a differential reception circuit 205 consisting of a pair of optical detectors and an amplifier, so that an electric signal I in which in-phase components in the DQPSK signal light are demodulated, is generated. Further, similarly to this, complementary two output powers output from an output stage coupler of the delay interferometer 202 is received by a differential reception circuit 206 consisting of a pair of optical detectors and an amplifier, so that an electric signal Q in which quadrature components in the DQPSK signal light are demodulated, is generated.
Moreover, as the delay interferometer used in the conventional optical receiver, other than the optical waveguide configuration, there has been known, for example, a configuration obtained by combining optical fiber fused couplers. Furthermore, there has been known a Mach-Zehnder delay interferometer configured by utilizing a propagation delay time difference between two intrinsic axes of a polarization-preserving fiber when a signal light subjected to the frequency shift keying (FSK) or the phase shift keying (PSK) is demodulated (refer to Japanese Unexamined Patent Publication No. 5-268159), although it is different from the delay interferometer having the object of demodulating the DQPSK signal light.
However, since the optical receiver having the conventional configuration as shown in FIG. 7 needs dual system delay interferometers each having the long optical path length, there is a problem in that the size of the optical receiver is enlarged. To be specific, in order to demodulate the DQPSK signal light of 40 Gb/s for example, since a delay time difference of about 50 ps corresponding to one symbol of the data signal of 20 Gb/s is generated by each of the delay interferometers, an optical path length difference of about 15 mm needs to be formed between the respective arms. In the case where such delay interferometers are realized by the optical waveguides formed on the silica substrates or the like, since it is necessary to arrange two optical waveguide substrates each having a large area, a large scale of the optical receiver is unavoidable. Moreover, in the optical receiver having the conventional configuration, since it is necessary to precisely coincide the operating point (phase difference) of one of the delay interferometers with π/4 and the operating point of the other delay interferometer with −π/4, there is a problem in that a technology for controlling with high accuracy an optical phase within each of the delay interferometers and an optical phase between the delay interferometers is required.
To the above problems, in the case where the miniaturization of the optical receiver is attempted by integrating the two delay interferometers into one planner lightwave circuit (PLC) chip, there is a possibility that the temperature distribution or the like occurs in the PLC chip having a large area, and as a result, the delay time or the interference operating point in each of the delay interferometers is deviated from a required value. In order to avoid such a possibility, the high accurate temperature designing or the high accurate packaging technology is needed, but may be an obstacle to the miniaturization and the low cost of the optical receiver.
Note, the configuration of the delay interferometer utilizing the above described polarization-preserving fiber can be effective means for solving the above problems. However, the conventional proposal merely aims at a single system delay interferometer corresponding to the FSK system or the PSK system. There has not been proposed a specific configuration considering up to problems particular to the DQPSK system caused by the conventional configuration which needs the dual system delay interferometers as described above.